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Communication Dans Un Congrès Année : 2020

Data-layout optimization based on Memory-Access-Pattern analysis for Source-Code Performance improvement

Résumé

With the rising impact of the memory wall, selecting the ade- quate data-structure implementation for a given kernel has become a performance-critical issue. This paper presents a new methodology to solve the data-layout decision problem by adapting an input implementation to the host hardware- memory hierarchy. The proposed method automatically iden- tifies, for a given input software, the most performing data- layout implementation for each selected variable by ana- lyzing the memory-access pattern. The proposed method is designed to be embedded within a general-purpose compiler. Experiments on PolybenchC benchmark, recursive-bilateral filter and jpeg-compression kernels, show that our method accurately determines the optimized data structure imple- mentation. These optimized implementations allow reaching an execution-time speed-up up to 48.9x and an L3-miss reduc- tion up to 98.1x, on an x86 processor implementing an Intel Xeon with three levels of data-caches using the least recently used cache-replacement policy.
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Dates et versions

cea-04505334 , version 1 (23-06-2024)

Identifiants

Citer

Riyane Sid Lakhdar, Henri-Pierre Charles, Maha Kooli. Data-layout optimization based on Memory-Access-Pattern analysis for Source-Code Performance improvement. SCOPES 2020 - 23rd International Workshop on Software and Compilers for Embedded Systems, May 2020, Sankt Goar, Germany. ⟨10.1145/3378678.3391874⟩. ⟨cea-04505334⟩
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